High-Speed Delay Line for Die-To-Die Interconnect

• Main Author: Li, Shenggao
• Format: Patent
• Language: English
• Published: 12.09.2024
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

Systems and methods are provided for a delay line circuit that comprises a delay line core and a first current mirror circuit. The delay line core includes a plurality of inverters connected in series. Each of the plurality of inverters is coupled to a first common node. The first current mirror circuit includes a first current source configured to generate a first digital-to-analog (DAC) current, a first transistor coupled to the first current source, and a plurality of first controlling transistors coupled to the first transistor and the first common node. The plurality of first controlling transistors generates a first mirror current at the first common node based on the first DAC current. A delay time of the delay line core is controlled based on the first mirror current.