SEMICONDUCTOR MEMORY APPARATUS AND TESTING METHOD THEREOF

A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array...

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Bibliographic Details
Main Authors Hsieh, Kuang-Chih, Wu, Chien-Min, Liao, Shao-Ching
Format Patent
LanguageEnglish
Published 22.08.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.
Bibliography:Application Number: US202318171666