DYNAMIC ERASE VOLTAGE STEP

Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordl...

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Bibliographic Details
Main Authors Yin, Chengkuan, Lu, Ching-Huang, Fukuzumi, Yoshiaki, Lai, Jiun-Horng, Prakash, Ronit Roneel, Shukla, Pitamber
Format Patent
LanguageEnglish
Published 22.08.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.
Bibliography:Application Number: US202418443584