FABRICATION METHOD FOR JFET WITH IMPLANT ISOLATION
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through...
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| Main Authors | , , , |
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| Format | Patent |
| Language | English |
| Published |
15.08.2024
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| Subjects | |
| Online Access | Get full text |
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| Abstract | Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region. |
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| AbstractList | Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region. |
| Author | Pidaparthi, Subhash Srinivas Drowley, Clifford Milano, Ray Edwards, Andrew P |
| Author_xml | – fullname: Edwards, Andrew P – fullname: Drowley, Clifford – fullname: Milano, Ray – fullname: Pidaparthi, Subhash Srinivas |
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| Notes | Application Number: US202418600234 |
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| RelatedCompanies | Semiconductor Components Industries, LLC |
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| Snippet | Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of... |
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| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| Title | FABRICATION METHOD FOR JFET WITH IMPLANT ISOLATION |
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