FABRICATION METHOD FOR JFET WITH IMPLANT ISOLATION
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
15.08.2024
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Subjects | |
Online Access | Get full text |
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Summary: | Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region. |
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Bibliography: | Application Number: US202418600234 |