BUFFER STRUCTURE WITH INTERLAYER BUFFER LAYERS FOR HIGH VOLTAGE DEVICE

Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channe...

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Bibliographic Details
Main Authors Chen, Kuei-Ming, Chen, Chi-Ming
Format Patent
LanguageEnglish
Published 08.08.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channel layer overlies the plurality of superlattice layers. An active layer overlies the channel layer. A first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. The first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.
Bibliography:Application Number: US202318329881