TRANSISTOR DEVICE HAVING A GATE SETBACK FROM A GATE DIELECTRIC

• Main Authors: Jong, Yu-Chang, Liu, Ruey-Hsin, Chen, Fei-Yun, Kung, Ta-Yuan, Yao, Chih-Wen Albert, Chu, Chen-Liang, Lei, Ming-Ta
• Format: Patent
• Language: English
• Published: 01.08.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.