SEMICONDUCTOR PACKAGE

A semiconductor package including first and second chip stacks each including semiconductor chips having an offset stack structure, the second chip stack horizontally spaced apart from the first chip stack, a first buffer chip on the substrate and at a side of the first chip stack, a second buffer c...

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Bibliographic Details
Main Authors LEE, Cheol-Woo, BAEK, Joonghyun, KANG, Hyungu, IM, Eunjeong, YOON, Sunghwan
Format Patent
LanguageEnglish
Published 25.07.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor package including first and second chip stacks each including semiconductor chips having an offset stack structure, the second chip stack horizontally spaced apart from the first chip stack, a first buffer chip on the substrate and at a side of the first chip stack, a second buffer chip on the substrate and at a side of the second chip stack, a connection substrate on the first and second chip stacks, a first mold layer covering the substrate, the first chip stack, and the second stack and exposing a top surface of the connection substrate, third and fourth chip stacks each including semiconductor chips having an offset stack structure on the first mold layer and, the fourth chip stack horizontally spaced apart from the third chip stack, and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack may be provided.
Bibliography:Application Number: US202318535339