SEMICONDUCTOR PACKAGE INCLUDING POST

A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating layer, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM....

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Bibliographic Details
Main Authors LEE, Jaekul, JANG, Hyungsun, SHIN, Minjeong, KIM, Gayoung
Format Patent
LanguageEnglish
Published 18.07.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating layer, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The post has a ring shape having an inner surface and an outer surface when viewed in a top view. A maximum width of the inner surface is less than a maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.
Bibliography:Application Number: US202418618133