MIDDLE OF THE LINE ARCHITECTURE WITH SUBTRACTIVE SOURCE/DRAIN CONTACT
A semiconductor device includes first and second nanosheet stacks above an upper surface of a semiconductor substrate, a first source/drain on an end of the first nanosheet stack, and a second source/drain on an end of the second nanosheet stack. A first gate stack wraps around individual channels o...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
04.07.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor device includes first and second nanosheet stacks above an upper surface of a semiconductor substrate, a first source/drain on an end of the first nanosheet stack, and a second source/drain on an end of the second nanosheet stack. A first gate stack wraps around individual channels of the first nanosheet stack and a second gate stack wraps around individual channels the second nanosheet stack. An interlayer dielectric covers the first and second nanosheet stacks, the first and second source/drains, and the first and second gate stacks. The semiconductor device further includes a first source/drain contact that contacts the first source/drain and a second source/drain contact that contacts the second source/drain. The first and second source/drain contacts extend continuously from the first and second source/drains, respectively, to an upper surface of the interlayer dielectric. |
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Bibliography: | Application Number: US202218148577 |