DISAGGREGATING A MEMORY SIDE CACHE DATA ARRAY AND CACHE CONTROLLER

In one embodiment, a semiconductor package comprises: a first die comprising: a plurality of cores; and memory circuitry comprising a memory controller and a memory side cache controller to maintain tag information and state information for a data array; and a second die coupled to the first die, th...

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Bibliographic Details
Main Authors Diamand, Israel, Anantaraman, Aravindh V, Osborne, Randy B, Bonen, Nadav
Format Patent
LanguageEnglish
Published 27.06.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In one embodiment, a semiconductor package comprises: a first die comprising: a plurality of cores; and memory circuitry comprising a memory controller and a memory side cache controller to maintain tag information and state information for a data array; and a second die coupled to the first die, the second die comprising the data array to cache data for at least one accelerator, the at least one accelerator remote from the first die. The memory side cache controller may be configured to control the data array. Other embodiments are described and claimed.
Bibliography:Application Number: US202218069249