INDEPENDENT CONTROL OF POWER, CLOCK, AND/OR RESET SIGNALS TO A PARTITIONED NODE

A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operab...

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Bibliographic Details
Main Authors Patel, Pravin S, Shah, Mehul, Cudak, Gary D, Parsonese, James
Format Patent
LanguageEnglish
Published 27.06.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operable as a second independent node and a system controller that is configured to selectively and independently control separate power, clock, and/or reset signals to the first plurality of components forming the first partitioned node and the second plurality of components forming the second partitioned node in response to receiving a first partitioning mode instruction from a baseboard management controller (BMC) that identifies a partitioned state and configured to selectively control the separate power, clock, and/or reset signals to the first and second pluralities of components in a unified manner in response to receiving a second partitioning mode instruction from the BMC that identifies a unified state.
Bibliography:Application Number: US202218087351