SIDEBAND INSTRUCTION ADDRESS TRANSLATION

Embodiments relate to sideband instruction address translation. According to an aspect, a computer-implemented method includes managing, within a processor, an instruction effective-to-real-address table (I-ERAT) separate from a main ERAT, where the I-ERAT has a smaller storage capacity than the mai...

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Bibliographic Details
Main Authors Levenstein, Sheldon Bernard, Nguyen, Dung Q, Orzol, Nicholas R, Gorti, Naga P, Lloyd, Bryan, Hrusecky, David A, Eickemeyer, Richard J, Karve, Mohit
Format Patent
LanguageEnglish
Published 20.06.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Embodiments relate to sideband instruction address translation. According to an aspect, a computer-implemented method includes managing, within a processor, an instruction effective-to-real-address table (I-ERAT) separate from a main ERAT, where the I-ERAT has a smaller storage capacity than the main ERAT. The method also includes indicating an I-ERAT hit based on determining that an instruction address for an instruction cache is stored in the I-ERAT, bypassing an arbitrator within the processor and sending a translated address from the I-ERAT to the instruction cache based on detecting the I-ERAT hit, and sending an address translation request through the arbitrator to the main ERAT based on an I-ERAT miss and writing a translation result of the main ERAT to the I-ERAT.
Bibliography:Application Number: US202218066480