SPARSITY-AWARE PERFORMANCE BOOST IN COMPUTE-IN-MEMORY CORES FOR DEEP NEURAL NETWORK ACCELERATION

Systems, apparatuses and methods may provide for technology that includes a compute-in-memory (CiM) enabled memory array to conduct digital bit-serial multiply and accumulate (MAC) operations on multi-bit input data and weight data stored in the CiM enabled memory array, an adder tree coupled to the...

Full description

Saved in:
Bibliographic Details
Main Authors Sayyaparaju, Sagar Varma, Subramoney, Sreenivas, Omer, Om Ji
Format Patent
LanguageEnglish
Published 20.06.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Systems, apparatuses and methods may provide for technology that includes a compute-in-memory (CiM) enabled memory array to conduct digital bit-serial multiply and accumulate (MAC) operations on multi-bit input data and weight data stored in the CiM enabled memory array, an adder tree coupled to the CiM enabled memory array, an accumulator coupled to the adder tree, and an input bit selection stage coupled to the CiM enabled memory array, wherein the input bit selection stage restricts serial bit selection on the multi-bit input data to non-zero values during the digital MAC operations.
Bibliography:Application Number: US202418590495