CLOCK RECOVERY WITH LOOP DELAY CANCELLATION

An illustrative integrated receiver circuit includes: a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling...

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Bibliographic Details
Main Authors SUN, JUNQING PHIL, HIDAKA, YASUO
Format Patent
LanguageEnglish
Published 06.06.2024
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:An illustrative integrated receiver circuit includes: a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a first feedback path that controls a sampling signal phase to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error; and a loop-delay cancellation circuit that buffers the sampling signal phase to reduce the residual phase error.
Bibliography:Application Number: US202218062382