DUAL POWER SUPPLIED MEMORY CELLS AND DETERMINISTIC RESET THEREOF FOR PROGRAMMABLE LOGIC DEVICES

Various techniques are provided to implement dual power supplied memory cells and deterministic reset thereof for programmable logic devices. In one example, a programmable logic device (PLD) includes a configuration memory including an array of memory cells arranged in rows and columns. The PLD fur...

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Bibliographic Details
Main Authors McLaury, Loren L, Sharpe-Geisler, Bradley A
Format Patent
LanguageEnglish
Published 06.06.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Various techniques are provided to implement dual power supplied memory cells and deterministic reset thereof for programmable logic devices. In one example, a programmable logic device (PLD) includes a configuration memory including an array of memory cells arranged in rows and columns. The PLD further includes a power supply circuit coupled to the configuration memory and configured to selectively couple, based on a reset control signal, a power supply to a first power supply line coupled to the array of memory cells. The array of memory cells is reset if the power supply is coupled to the first power supply line. The power supply circuit is further configured to provide power on a second power supply line to the array of memory cells. Related methods and devices are provided.
Bibliography:Application Number: US202318525216