SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

• Main Author: JANG, DONGHYEON
• Format: Patent
• Language: English
• Published: 30.05.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A semiconductor package includes a lower redistribution wiring layer having first redistribution wirings stacked in at least two layers, a semiconductor chip disposed on the lower redistribution wiring layer and electrically connected to the first redistribution wirings, a sealing member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings, and an upper redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of through vias. Each of the first redistribution wirings includes a barrier layer pattern, a seed layer pattern and a plating pattern sequentially stacked. From a plan view, a sidewall of the barrier layer pattern extends laterally beyond a sidewall of the seed layer pattern.