VERTICAL DIGIT LINES FOR SEMICONDUCTOR DEVICES

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates op...

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Bibliographic Details
Main Authors Hwang, Sangmin, Lee, Si-Woo
Format Patent
LanguageEnglish
Published 23.05.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.
Bibliography:Application Number: US202418428581