PROCESS WINDOW CONTROL FOR GATE FORMATION IN SEMICONDUCTOR DEVICES

A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an...

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Main Authors LIN, Shih-Yao, CHEN, Chen-Ping, CHANG, Ming-Ching, KAO, Kuei-Yu, LIN, Chih-Han, CHEN, Chao-Cheng
Format Patent
LanguageEnglish
Published 23.05.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.
Bibliography:Application Number: US202418426859