PROCESS WINDOW CONTROL FOR GATE FORMATION IN SEMICONDUCTOR DEVICES
A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an...
Saved in:
Main Authors | , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
23.05.2024
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit. |
---|---|
Bibliography: | Application Number: US202418426859 |