DISPLAY PROCESSING UNIT (DPU) PIXEL RATE BASED ON DISPLAY REGION OF INTEREST (ROI) GEOMETRY

Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a CPU. The apparatus may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all content in the first...

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Bibliographic Details
Main Authors MARCHYA, Dileep, PULLAKAVI, Srinivas, KOMANDURU V, Padmanabhan
Format Patent
LanguageEnglish
Published 23.05.2024
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DISPLAY
EDUCATION
PHYSICS
SEALS
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Summary:Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a CPU. The apparatus may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all content in the first frame, where the partial frame update for the first frame is associated with a panel ROI of the first frame. The apparatus may also calculate a margin time period between the first update time and a subsequent Vsync time. Further, the apparatus may transmit, based on the margin time period, a first indication of a subsequent frame transfer interrupt time. The apparatus may also transmit, to a DPU, a second indication to transfer the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting at the subsequent frame transfer interrupt time.
Bibliography:Application Number: US202218057750