PACKAGE EDGE PASSIVE COMPONENT ARRAY FOR IMPROVED POWER INTEGRITY

The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of th...

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Bibliographic Details
Main Authors CHEAH, Bok Eng, JAIN, Amit, KONG, Jackson Chung Peng, KUAN, Chin Lee, SHEKHAR, Sameer
Format Patent
LanguageEnglish
Published 02.05.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.
Bibliography:Application Number: US202218050527