MEMORY WITH ERROR CHECKING AND CORRECTING UNIT
A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the mu...
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| Main Authors | , , , , , , |
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| Format | Patent |
| Language | English |
| Published |
02.05.2024
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data. |
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| AbstractList | A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data. |
| Author | SHANG, Weibing Zhang, Liang Ji, Kangling Wang, Ying Li, Hongwen Chi, Sungsoo Wu, Daoxun |
| Author_xml | – fullname: Ji, Kangling – fullname: Zhang, Liang – fullname: Chi, Sungsoo – fullname: Wu, Daoxun – fullname: Li, Hongwen – fullname: SHANG, Weibing – fullname: Wang, Ying |
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| Notes | Application Number: US202318393820 |
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| RelatedCompanies | CHANGXIN MEMORY TECHNOLOGIES, INC |
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| Snippet | A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage... |
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| Title | MEMORY WITH ERROR CHECKING AND CORRECTING UNIT |
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