MEMORY WITH ERROR CHECKING AND CORRECTING UNIT

A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the mu...

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Bibliographic Details
Main Authors Ji, Kangling, Zhang, Liang, Chi, Sungsoo, Wu, Daoxun, Li, Hongwen, SHANG, Weibing, Wang, Ying
Format Patent
LanguageEnglish
Published 02.05.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.
Bibliography:Application Number: US202318393820