NONVOLATILE MEMORY DEVICE SUPPORTING GIDL ERASE OPERATION

Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed,...

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Bibliographic Details
Main Authors SON, Yong-Wan, JOO, Sang-Hyun, HAM, Dae Sik
Format Patent
LanguageEnglish
Published 02.05.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.
Bibliography:Application Number: US202318364126