INTELLIGENT EXPOSURE OF HARDWARE LATENCY STATISTICS WITHIN AN ELECTRONIC DEVICE OR SYSTEM

A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The...

Full description

Saved in:
Bibliographic Details
Main Authors Manevich, Natan, Aisman, Shay, Levi, Dotan David, Almog, Ariel, Koren, Ran Avraham
Format Patent
LanguageEnglish
Published 25.04.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
Bibliography:Application Number: US202218074751