CHAINED ACCELERATOR OPERATIONS WITH STORAGE FOR INTERMEDIATE RESULTS

A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory loc...

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Bibliographic Details
Main Authors HUGHES, Christopher J, GAYEN, Saurabh, HEINECKE, Alexander F, KAKAIYA, Utkarsh Y
Format Patent
LanguageEnglish
Published 18.04.2024
Subjects
CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, generate first intermediate data, and store the first intermediate data to a storage. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data from the storage, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.
Bibliography:Application Number: US202217967768