HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS

A method for fabricating and a structure comprising one or more transistors where a transistor includes one or more nanosheets formed based on one or more layers of a nanosheet material. A layer of shell material can at least partly surround the one or more nanosheets to form one or more channels of...

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Bibliographic Details
Main Authors Fulford, H. Jim, Gardner, Mark I
Format Patent
LanguageEnglish
Published 11.04.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method for fabricating and a structure comprising one or more transistors where a transistor includes one or more nanosheets formed based on one or more layers of a nanosheet material. A layer of shell material can at least partly surround the one or more nanosheets to form one or more channels of the transistor. A gate structure of the transistor can at least partly surround each of the one or more channels. The gate structure can include a gate dielectric disposed between the layer of the shell material and a gate metal of the gate structure for each of the nanosheets, where the shell material can include a charge carrier mobility that is greater than a charge carrier mobility of the nanosheet material.
Bibliography:Application Number: US202217962222