REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS

Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a sec...

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Bibliographic Details
Main Authors THOZIYOOR, Shyamkumar, SUH, Jungwon, DESHMUKH, Pankaj, PALACHARLA, Subbarao
Format Patent
LanguageEnglish
Published 04.04.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.
Bibliography:Application Number: US202318527713