VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY

• Main Authors: Hwang, David K, Nakamura, Yoshitaka, Walters, Glen H, Sills, Scott E, Ma, Yuanzhi, Lee, Si-Woo
• Format: Patent
• Language: English
• Published: 21.03.2024

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.