ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION

Disclosed are techniques for on-chip electromagnetic interference (EMI) shielding. In an aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of...

Full description

Saved in:
Bibliographic Details
Main Authors DUTTA, Ranadeep, KIM, Jonghae, LAN, Je-Hsiung
Format Patent
LanguageEnglish
Published 21.03.2024
Subjects
ANTENNAS, i.e. RADIO AERIALS
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:Disclosed are techniques for on-chip electromagnetic interference (EMI) shielding. In an aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield around the first side of the noise-sensitive device, and a second metallization layer disposed on a second side of the noise-sensitive device opposite the first side of the noise-sensitive device, wherein the second metallization layer includes one or more conductive routing layers, and wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield around the second side of the noise-sensitive device.
Bibliography:Application Number: US202217932788