SACRIFICIAL LAYER FOR FORMING MERGED HIGH ASPECT RATIO CONTACTS IN 3D NAND MEMORY DEVICE

A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first...

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Main Authors KANG, Sung-Kwan, VENKATASUBRAMANIAN, Eswaranand, CHILD, Amy, PRANATHARTHIHARAN, Balasubramanian, KAMATH, Sanjay G, LEE, Soonil, GUGGILLA, Srinivas, KANG, Chang Seok, MALLICK, Abhijit B, WANG, Jialiang
Format Patent
LanguageEnglish
Published 14.03.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.
Bibliography:Application Number: US202318238954