EMBEDDED CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the...

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Bibliographic Details
Main Authors FENG, LEI, HUANG, BENXIA, FENG, JINDONG, WANG, WENSHI, CHEN, XIANMING
Format Patent
LanguageEnglish
Published 14.03.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.
Bibliography:Application Number: US202318389264