MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other t...
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Main Authors | , , , , , |
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Format | Patent |
Language | English |
Published |
14.03.2024
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Subjects | |
Online Access | Get full text |
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