MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other t...
Saved in:
Main Authors | , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
14.03.2024
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids. |
---|---|
Bibliography: | Application Number: US202318514254 |