MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS

• Main Authors: Shue, Shau-Lin, Su, Li-Lin, Yang, Tai-I, Liu, Hsiang-Wei, Wu, Yung-Hsu, Chu, Wei-Chen
• Format: Patent
• Language: English
• Published: 14.03.2024
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CINEMATOGRAPHY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.