APPARATUSES AND METHODS FOR TRAINING OPERATIONS

A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may...

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Bibliographic Details
Main Authors SONG, KEUN SOO, SAITO, SHUNICHI, MATSUI, YOSHINORI, TAKAHASHI, HIROKI, NAGASHIMA, OSAMU
Format Patent
LanguageEnglish
Published 07.03.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.
Bibliography:Application Number: US202318353639