PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS

• Main Authors: Pasdast, Gerald S, Siers, Scott E, Seangatith, Jiraporn, Liff, Shawna M, Elsherbini, Adel A, Tiagaraj, Sathya Narasimman, Kabir, Mohammad Enamul, Braunisch, Henning, Jun, Kimin, Swan, Johanna M
• Format: Patent
• Language: English
• Published: 22.02.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.