WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME

A wafer-level packaging structure and a method for preparing the same are provided, the wafer-level packaging structure includes at least a molding layer and a 3D IPD structure fabricated in the molding layer. The wafer-level packaging structure of the present disclosure can integrate various electr...

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Bibliographic Details
Main Authors Chen, Yenheng, Lin, Chengchung
Format Patent
LanguageEnglish
Published 15.02.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A wafer-level packaging structure and a method for preparing the same are provided, the wafer-level packaging structure includes at least a molding layer and a 3D IPD structure fabricated in the molding layer. The wafer-level packaging structure of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.
Bibliography:Application Number: US202318344218