MEMORY DEVICE THAT PERFORMS ERASE OPERATION TO PRESERVE DATA RELIABILITY

A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one...

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Bibliographic Details
Main Authors PARK, Sehwan, PARK, Ilhan, SEO, Youngdeok, KIM, Jinyoung, SHIN, Dongmin
Format Patent
LanguageEnglish
Published 01.02.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.
Bibliography:Application Number: US202318378540