MEMORY ROW-HAMMER MITIGATION

Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region...

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Bibliographic Details
Main Authors Kerstetter, Bryan David, Wilson, Alan J, Morgan, Donald Martin
Format Patent
LanguageEnglish
Published 01.02.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an "ON" state). Accordingly, the value of the counter may be maintained across power cycles.
Bibliography:Application Number: US202217877592