THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTERCONNECT

Methods and apparatus relating to a Universal Chiplet Interconnect Express™ (UCIe™)-Three Dimensional (UCIe-3D™) interconnect which may be utilized as an on-package interconnect are described. In one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet...

Full description

Saved in:
Bibliographic Details
Main Authors Onufryk, Peter Z, Pasdast, Gerald S, Tiagaraj, Sathya Narasimman, Das Sharma, Debendra
Format Patent
LanguageEnglish
Published 25.01.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:Methods and apparatus relating to a Universal Chiplet Interconnect Express™ (UCIe™)-Three Dimensional (UCIe-3D™) interconnect which may be utilized as an on-package interconnect are described. In one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet on a semiconductor package to a second physical layer module of a second chiplet on the semiconductor package. A first Network-on-chip Controller (NoC) logic circuitry controls the first physical layer module. A second NoC logic circuitry controls the second physical layer module. Other embodiments are also claimed and disclosed.
Bibliography:Application Number: US202318479014