METHOD, SYSTEM AND DEVICE OF SERIALIZING AND DE-SERIALIZING THE DELIVERY OF SCAN TEST DATA THROUGH CHIP I/O TO REDUCE THE SCAN TEST DURATION OF AN INTEGRATED CIRCUIT

An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated...

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Bibliographic Details
Main Authors Zhong, Zhanwei, Biswas, Sounil, Wangoo, Amit
Format Patent
LanguageEnglish
Published 25.01.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.
Bibliography:Application Number: US202217869495