DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon ch...

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Bibliographic Details
Main Authors Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Format Patent
LanguageEnglish
Published 11.01.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
Bibliography:Application Number: US202318470652