EXAMINATION OF A HOLE FORMED IN A SEMICONDUCTOR SPECIMEN

A system of examination of a semiconductor specimen, comprising a processor and memory circuitry (PMC) configured to:obtain an image of a hole formed in the semiconductor specimen, wherein the hole exposes at least one layer of a plurality of layers of the semiconductor specimen,segment the image in...

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Main Authors KEREM, Omer, GOLOV, Asaf, SOMMER, Elad, VERESCHAGIN, Vadim, KLEBANOV, Grigory, BEN-HARUSH, Ilan, BISTRITZER, Rafael, KRIS, Roman
Format Patent
LanguageEnglish
Published 28.12.2023
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A system of examination of a semiconductor specimen, comprising a processor and memory circuitry (PMC) configured to:obtain an image of a hole formed in the semiconductor specimen, wherein the hole exposes at least one layer of a plurality of layers of the semiconductor specimen,segment the image into a plurality of regions,generate at least one of:data Dpix_intensity informative of one or more pixel intensities of one or more regions of the plurality of regions,data Dgeometry informative of one or more geometrical properties of one or more regions of the plurality of regions,feed at least one of Dpix_intensity or Dgeometry to a trained classifier to obtain an output, wherein the output of the trained classifier is usable to determine whether the hole ends at a target layer of the plurality of layers.
Bibliography:Application Number: US202217848360