Method of Fabricating Thin, Crystalline Silicon Film and Thin Film Transistors

A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon lay...

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Main Author Kakkad, Ramesh Kumar Harjivan
Format Patent
LanguageEnglish
Published 28.12.2023
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Abstract A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon layer can be formed on the substrate, the phosphorus doped silicon layer on the intrinsic silicon layer, and the nickel patterns on the phosphorus doped silicon layer. The structure is annealed to crystallize the phosphorus doped silicon and intrinsic silicon layers. A method of forming a crystalline silicon layer of a TFT device includes forming a first silicon film, forming a phosphorus doped silicon film on the first silicon film, forming a nickel film on the phosphorus doped silicon film, and annealing the structure to crystallize the phosphorus doped silicon and first silicon films. The first silicon and phosphorous doped silicon films are amorphous at formation.
AbstractList A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon layer can be formed on the substrate, the phosphorus doped silicon layer on the intrinsic silicon layer, and the nickel patterns on the phosphorus doped silicon layer. The structure is annealed to crystallize the phosphorus doped silicon and intrinsic silicon layers. A method of forming a crystalline silicon layer of a TFT device includes forming a first silicon film, forming a phosphorus doped silicon film on the first silicon film, forming a nickel film on the phosphorus doped silicon film, and annealing the structure to crystallize the phosphorus doped silicon and first silicon films. The first silicon and phosphorous doped silicon films are amorphous at formation.
Author Kakkad, Ramesh Kumar Harjivan
Author_xml – fullname: Kakkad, Ramesh Kumar Harjivan
BookMark eNqNiksKwjAQQLPQhb87DLhV0EYPIMXgRjet6zKmUzsQZ0qSjbdX1AO4eY8Hb2pGokITczlT7rUF7cDhLbLHzHKHumdZQRmfKWMILAQVB_Yq4Dg8AKX9LN-qI0rilDWmuRl3GBItfp6ZpTvW5WlNgzaUBvQklJtrVWwKu3tjbw9b-9_1AqAvOEE
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US2023420253A1
GroupedDBID EVB
ID FETCH-epo_espacenet_US2023420253A13
IEDL.DBID EVB
IngestDate Fri Jul 19 13:13:53 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US2023420253A13
Notes Application Number: US202318466644
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231228&DB=EPODOC&CC=US&NR=2023420253A1
ParticipantIDs epo_espacenet_US2023420253A1
PublicationCentury 2000
PublicationDate 20231228
PublicationDateYYYYMMDD 2023-12-28
PublicationDate_xml – month: 12
  year: 2023
  text: 20231228
  day: 28
PublicationDecade 2020
PublicationYear 2023
RelatedCompanies Kakkad Ramesh Kumar Harjivan
RelatedCompanies_xml – name: Kakkad Ramesh Kumar Harjivan
Score 3.5196676
Snippet A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Method of Fabricating Thin, Crystalline Silicon Film and Thin Film Transistors
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231228&DB=EPODOC&locale=&CC=US&NR=2023420253A1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD6MKeqbTsXLlIDSJ4suW28PRVy7MoRdsJvsbTRrIoOZjrUi_ntPsk73tJfQNCEkoaffObl8H8C9rbaCHPXxciHMluMyM0mpZ1LBnmYCYzGq1Rp6fbs7br1OrEkFFpu7MJon9FuTI6JFzdDeC_2_Xv4vYoX6bGX-yOb4KnuORn5olNExOiuUukbY9jvDQTgIjCDwx7HRf9NlLUys5gvGSnvKkVZM-533trqXstwGlegY9ofYnixOoMJlDQ6DjfZaDQ565ZY3PpbWl59Cv6flnkkmSJSwtb6P_CBKevOBBKsfdPQUwzYn8RxHkUkSzRefJJGprrLOaWzS1CD5GdxFnVHQNbFj0795mI7j7VE0z6EqM8kvgDDHs5lAPGpQjgAtPJ42kpQ7npc0G8JyL6G-q6Wr3cXXcKSy6gwHdetQLVZf_AaRuGC3egJ_ASp-i-g
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1dT8IwFL0haMQ3RY0fqE00e3JROmDbAzGysaCyQQQMb2RlrSHBjsCM8d97W0B54qVZd5tmbXZ7evpxD8BtTW0F2ern5UKYFdthZpxQ16SCPYwFcjGq1RrCqNYaVF6G1WEOpuu7MDpO6LcOjogeNUZ_z_R4PftfxPL12crFPZvgq_Qx6Nd9Y8WOcbJCqWP4jXqz2_E7nuF59UHPiN60rYJJ1XpCrrRjIynUZOm9oe6lzDZBJTiA3S7WJ7NDyHFZhIK31l4rwl642vLGx5X3LY4gCrXcM0kFCWK21PeRH0RJb94Rb_6DEz0VYZuT3gRbkUoSTKafJJaJLrLMaWzSoUEWx3ATNPtey8QPG_31w2jQ22yFdQJ5mUp-CoTZbo0JxKMy5QjQwuVJOU647bqxVRZV5wxK22o6326-hkKrH7ZH7efo9QL2lUmd56BOCfLZ_ItfIipn7Ep35i_aZI7S
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+of+Fabricating+Thin%2C+Crystalline+Silicon+Film+and+Thin+Film+Transistors&rft.inventor=Kakkad%2C+Ramesh+Kumar+Harjivan&rft.date=2023-12-28&rft.externalDBID=A1&rft.externalDocID=US2023420253A1