LOW-POWER STATIC RANDOM ACCESS MEMORY

A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of...

Full description

Saved in:
Bibliographic Details
Main Authors SATO, Katsuyuki, SAIJAGAN, Saijagan, ROHLMAN, Joseph Francis, SNELGROVE, William Martin
Format Patent
LanguageEnglish
Published 28.12.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
Bibliography:Application Number: US202318235954