SECURITY SUBSYSTEM FOR REMOTE ATTESTATION

Techniques for providing remote attestation at an integrated circuit device are described. The integrated circuit device may include a memory. The integrated circuit device may also include a write bitmap comprising a bitmap that tracks the write addresses of detected memory write operations to the...

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Bibliographic Details
Main Authors Gummalla, Samatha, Rahbar, Ali, Chang, Diana, Choi, Donghyun, Ananthateerta, Gururaj, Solanki, Utpal Vijaysinh, Quach, Nhon Toai
Format Patent
LanguageEnglish
Published 28.12.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques for providing remote attestation at an integrated circuit device are described. The integrated circuit device may include a memory. The integrated circuit device may also include a write bitmap comprising a bitmap that tracks the write addresses of detected memory write operations to the memory. The integrated circuit device may further include a security subsystem configured to send one or more address ranges of interest to the write bitmap and obtain a bitmap status from the write bitmap indicating that a write address within the one or more address ranges of interest was detected.
Bibliography:Application Number: US202217852083