SECURITY SUBSYSTEM FOR EXECUTION VERIFICATION

Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the...

Full description

Saved in:
Bibliographic Details
Main Authors Gummalla, Samatha, Kang, Jonathan, Rahbar, Ali, Ananthateerta, Gururaj, Solanki, Utpal Vijaysinh, Quach, Nhon Toai, Wright, John Charles
Format Patent
LanguageEnglish
Published 28.12.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.
Bibliography:Application Number: US202217852073