TWO-DIMENSIONAL PMOS DEVICES FOR PROVIDING CMOS IN BACK-END LAYERS OF INTEGRATED CIRCUIT DEVICES

• Main Authors: Naylor, Carl Hugo, Steinhardt, Rachel A, Maxey, Kirby, Lee, Sudarat, Avci, Uygar E, Clendenning, Scott B, Dorow, Chelsey, Penumatcha, Ashish Verma, O'Brien, Kevin P, Kitamura, Ande
• Format: Patent
• Language: English
• Published: 21.12.2023
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES

In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).